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51 SCM minimum system board STC89C52 STC89-STC12 core development board #V10 1226181
51 SCM minimum system board STC89C52 STC89-STC12 core development board #V10 1226181
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7,500 IQD
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7,500 IQD
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51 SCM minimum system board STC89C52 STC89-STC12 core development board
بورد تطويري مبني على شريحة STC89-STC12
يتوفر بسعر 7,500 دينار
Description
Main performance of STC12C5A60S2 series:
● High speed: 1 clock/machine cycle, enhanced 8051 core, 6~12 times faster than ordinary 8051
Wide voltage: 5.5~4.0V, 2.1~3.6V (STC12LE5A60S2 series)
● Add the second reset function pin/P4.6 (high reliable reset, adjustable reset threshold voltage, this function is not required when the frequency is<12MHz)
The external power failure detection circuit/P4.6 is added, which can save the data into EEPROM in time when power failure occurs
No need to operate EEPROM
● Low power consumption design: idle mode (can be awakened by any interrupt)
Low power consumption design: power-off mode (can be awakened by external interrupt), can support falling edge/rising edge and remote wake-up
● Pin supporting power failure wake-up: P3.2/NTO, P3.3/INTT, T0/P3.4. T1/P3.5, RxD/P3.0. P1.3/CCP0 (or
P4.2/CCP0), P1.4/CCP1 (or P4.3/CCP1), EX_ LVD/P4.6
● Operating frequency: 0~35MHz, equivalent to common 8051: 0~420MHz
● Clock: optional external product or internal R/C oscillator, set when ISP downloads the programming user program
● 8/16/32/40/48/56/60/62K byte on-chip Flash program memory, with more than 100000 erasures
● 1280 byte on-chip RAM data memory
● Large capacity on-chip EEPROM function with more than 100000 erasures
ISPIAP, programmable in system/programmable in application, without programmer/emulator
8-channel, 10 bit high-speed ADC, speed up to 250000 times/second, 2-channel Pu can also be used as 2-channel D/A
2-channel capture/comparison unit (CCP/PCAPWM),
---It can also be used to realize 2 timers or 2 external interrupts (support rising edge/falling edge interrupts)
● Two 16 bit timers (compatible with common 8051 timer TO/T1), and two more timers can be realized by two-way PCA
. Programmable clock output function (TO outputs clock in EP3.4, TI outputs clock in P3.5, BRT outputs clock in EP1.0
Hardware watchdog (WDT)
Independent baud rate generator
● SPI high-speed synchronous serial communication interface
Dual serial port, full duplex asynchronous serial port (UART), compatible with common 8051 serial port, time-sharing multiplexing can be used in three groups
● Advanced instruction set structure, compatible with common 8051 instruction set, with hardware multiplication/division instructions
● Universal I0 port (36/40/44), after reset, it is quasi two-way port/weak pull-up port (common 8051 traditional I/O port)
It can be set into four modes: quasi two-way port/weak pull-up, strong push-pull/strong pull-up, only for input high resistance, open drain
The drive capacity of each I/O port can reach 20mA, but it is recommended that the entire chip not exceed 120mA
Materials
Materials
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Shipping & Returns
Dimensions
Dimensions
Care Instructions
Care Instructions
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